-----------------------------=----------------------------------------- -- E - Z R e a d V H D L -----------------------------=----------------------------------------- -- template.vhd : Lab template -- LAB : 0 -- PROJECT : "11" pattern detector -- ENTITY : pattern -- ARCHITECTURE : pattern_ar (Architecture) -----------------------------=----------------------------------------- -- owner : Mouli Subramanian -- E-Mail : mouli@asu.edu -- department : Electrical Engineering -- design started : Dec 18, 2000 -----------------------------=----------------------------------------- -- Description: -- The state machine is designed to control a "11" pattern detector from -- a serial stream of '1's and '0's coming in as input. The state machine -- flags an output "DETECT" whenever a pattern "11" is detected. -- Type of state machine : MEALY -- Number of states : TWO -- Encoding style used : BINARY -- Number of flops inferred : TWO (one for the current st. logic and one -- for registering the output) -- Example waveform -- ---------------- -- ____ ____ ____ ____ ____ ____ -- | | | | | | | | | | | | -- CLK _| |____| |___| |____| |____| |____| |____ -- _________ ____________________________ -- | | | | -- DIN | |________| |_________ -- __________ -- | | --DETECT______________________________| |__________________ -- To keep it simple, the state machine output, "DETECT" becomes '1' only -- for one clock cycle (representing "11" pattern detection). -- If you carefully observe the waveform above, you will see three consequtive -- '1's on the "DIN" line. In this case, the DETECT signal becomes asserted only -- upon seeing the first two '1's (of the three '1's in a row). In other -- words, the LSB '1' of a detected "11" pattern will not be taken into -- account as one of the '1's for the next pattern detection, even though -- the subsequent DIN bit (the bit that comes in right after the detected -- "11" pattern) is a '1'. This is done to avoid the assertion of DETECT -- for 2 consequtive clock cycles. -----------------------------=----------------------------------------- -- libraries -----------------------------=----------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --*************************=***************************************** -- E N T I T Y --*************************=***************************************** entity pattern is port ( RST_N : in std_logic; CLK : in std_logic; DIN : in std_logic; DETECT : out std_logic ); end pattern; --*************************=***************************************** -- A R C H I T E C T U R E --*************************=***************************************** architecture pattern_ar of pattern is -------------------------=----------------------------------------- -- constants -------------------------=----------------------------------------- constant SIGNATURE_C : std_logic_vector(1 downto 0) := "11"; -------------------------=----------------------------------------- -- circuit internal signals and type declarations -------------------------=----------------------------------------- type fsm_st is (IDLE_ST, ONE_DET_ST); signal cur_st : fsm_st; signal nxt_st : fsm_st; ---------------------------=----------------------------------------- -- architecture body ---------------------------=----------------------------------------- begin ---------------------------=----------------------------------------- -- Process to clock the state register ---------------------------=----------------------------------------- cur_st_pr: process (clk, rst_n) begin if (rst_n = '0') then cur_st <= IDLE_ST; elsif (clk'event and clk = '1') then cur_st <= nxt_st; end if; end process cur_st_pr; ---------------------------=----------------------------------------- -- Process to realise the combinational logic for the next state ---------------------------=----------------------------------------- nxt_st_pr: process (cur_st, din) begin CASE cur_st is when IDLE_ST => if (din = '1') then nxt_st <= ONE_DET_ST; else nxt_st <= cur_st; end if; when ONE_DET_ST => nxt_st <= IDLE_ST; when OTHERS => nxt_st <= IDLE_ST; end CASE; end process nxt_st_pr; ---------------------------=----------------------------------------- -- Process to register all the state machine outputs ---------------------------=----------------------------------------- reg_pr: process (RST_N, clk) begin if (RST_N = '0') then detect <= '0'; elsif (clk'event and clk = '1') then CASE nxt_st is when IDLE_ST => detect <= '0'; when ONE_DET_ST => if (din = '1') then detect <= '1'; else detect <= '0'; end if; when OTHERS => detect <= '0'; end CASE; end if; end process reg_pr; END pattern_ar; -- END OF ARCHITECTURE ------------------------------=----------------------------------------- -----------------------------=----------------------------------------- -- E - Z R e a d V H D L -----------------------------=----------------------------------------- -- pattern_tb.vhd : test bench template -- LAB : 0 -- PROJECT : "11" pattern detector -- ENTITY : pattern_tb -- ARCHITECTURE : pattern_tb_ar (Architecture) -----------------------------=----------------------------------------- -- owner : Mouli Subramanian -- E-Mail : mouli.subramanian@ASU.edu -- department : Electrical Engineering -- design started : Dec 20 2000 -----------------------------=----------------------------------------- -----------------------------=----------------------------------------- -- libraries -----------------------------=----------------------------------------- library IEEE; use IEEE.std_logic_1164.all; --*************************=***************************************** -- E N T I T Y --*************************=***************************************** entity pattern_tb is end pattern_tb; --*************************=***************************************** -- A R C H I T E C T U R E --*************************=***************************************** architecture pattern_tb_ar of pattern_tb is -------------------------=----------------------------------------- -- timing constants -------------------------=----------------------------------------- constant TCLKH_C : time := 5 ns; constant TCLKL_C : time := TCLKH_C; constant TCLKHL_C : time := TCLKH_C + TCLKL_C; constant TRDELAY_C : time := TCLKL_C; constant TRHOLD_C : time := 1 ns; -------------------------=----------------------------------------- -- internal signal declarations -------------------------=----------------------------------------- signal rst_n : std_logic; signal clk : std_logic; signal din : std_logic; signal detect : std_logic; signal vector : std_logic_vector (15 downto 0); -------------------------=----------------------------------------- -- component -------------------------=----------------------------------------- component pattern port ( RST_N : in std_logic; CLK : in std_logic; DIN : in std_logic; DETECT : out std_logic ); end component; ---------------------------=----------------------------------------- -- architecture body ---------------------------=----------------------------------------- begin -------------------------=----------------------------------------- -- instantiations -------------------------=----------------------------------------- pattern_ins : pattern port map ( RST_N => rst_n, CLK => clk, DIN => din, DETECT => detect ); -------------------------=----------------------------------------- -- process: RST_N reset generation -------------------------=----------------------------------------- RST_PR : process begin rst_n <= '1'; wait for TRDELAY_C; rst_n <= '0'; wait until (clk'event and clk = '1'); wait until (clk'event and clk = '1'); wait for TRHOLD_C; rst_n <= '1'; wait; -- wait forever end process RST_PR; -------------------------=----------------------------------------- -- process: CLK clock generation -------------------------=----------------------------------------- CLK_PR : process begin if (now = 0 ns) then clk <= '0'; end if; wait for TCLKL_C; clk <= '1'; wait for TCLKH_C; clk <= '0'; end process CLK_PR; -------------------------=----------------------------------------- -- process: sim and stop -------------------------=----------------------------------------- STIMULUS_PR: process begin --.....................=....................................... -- intitialize data-in input --.....................=....................................... DIN <= '0'; vector <= "0101110010110111"; --.....................=....................................... -- reset cycle --.....................=....................................... wait until (rst_n = '1'); wait until (rst_n = '0'); wait until (clk'event and clk = '1'); wait until (clk'event and clk = '1'); --.....................=....................................... -- test data set #1 --.....................=....................................... for i in 1 to 16 loop din <= vector(15); vector (15 downto 0) <= vector (14 downto 0) & '0'; wait for (TCLKHL_C); end loop; --.....................=....................................... -- test data set #2 --.....................=....................................... wait until (clk'event and clk = '1'); wait until (clk'event and clk = '1'); wait until (clk'event and clk = '1'); vector <= "1111111011111111"; wait until (clk'event and clk = '1'); for i in 1 to 16 loop din <= vector(15); vector (15 downto 0) <= vector (14 downto 0) & '0'; wait for (TCLKHL_C); end loop; --.....................=....................................... -- test data set #3 --.....................=....................................... wait until (clk'event and clk = '1'); wait until (clk'event and clk = '1'); wait until (clk'event and clk = '1'); vector <= "0000000110000000"; wait until (clk'event and clk = '1'); for i in 1 to 16 loop din <= vector(15); vector (15 downto 0) <= vector (14 downto 0) & '0'; wait for (TCLKHL_C); end loop; --.....................=....................................... -- end simulation --.....................=....................................... assert (FALSE) report "End of Stimulus" severity failure; wait; end process STIMULUS_PR; end pattern_tb_ar; -- end of architecture