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Class Dates
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Syllabus Covered
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Jan 15, 17, 22, 24
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- Digital Logic Design
Fundamentals
- Design Flow
Methodology
- VHDL - What is it and
Why ?
- Lab 1 assigned on Jan 22
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Jan 29
(Tuesday)
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- Quiz 1 (25 minutes)
- Language Fundamentals
(Entity, Architecture, Sequential and Concurrent Statements,
Configuration)
- Lab 1 due today
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Jan 31
(Thursday)
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- Test benches
- Sequential Statements
(IF, FOR LOOP, CASE, FOR GENERATE, Assertion/Report)
- Concurrent Statements
- Lab 2 assigned (Multiplexer, Combologic,
test bench)
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Feb 5
(Tuesday)
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- Modeling Latches,
Flip-flops, Multiplexers, Address decoder, Shift register, Counters
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Feb 7
(Thursday)
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(Syllabus: All the topics
discussed from Jan 15, 2002 to Feb 5, 2002)
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Feb 12
(Tuesday)
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- Test 1 Review
- Description of a
Register Bank
- Procedure-based test
bench
- Lab 2 due today
- Lab 3 assigned today
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Feb 14
(Thursday)
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- Scalar data types and
Operations
- Composite Data types
and Operations
- Arrays - Constrained,
Unconstrained, constant and array mappings
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Feb 19
(Tuesday)
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- Test 1
- Packages
- Resolved Signals
- Generics
- Shared variables
- Lab 4 assigned today
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Feb 21
(Thursday)
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- State Machines (Definition,
types, examples and Industry rules)
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Feb 26
(Tuesday)
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- Discussion on
Peter's paper - Ten Commandments of Excellent Design
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Feb 28
(Thursday)
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- Memory Modeling
using Dynamic Allocation
- File I/O, Access
types and records
- QUIZ 3(what ever was covered on Feb 21st and all
questions asked in test 1)
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Mar 5
(Tuesday)
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- Lab 4 due today
- Coding Tips and
techniques for synthesizable, reusable VHDL
- Lab 5 assigned today
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Mar 7
(Thursday)
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- Coding Tips for creating
synthesizable, reusable VHDL (excerpts from paper by Subbu, Peter and
Ken)
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Mar 12, 14
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SPRING BREAK
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Mar 19
(Tuesday)
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- Lab 5 due today
- Lab 6 assigned today (FIFO)
- Project
Specifications discussed briefly
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Mar 21
(Thursday)
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- Project
Specifications Discussion continues
- How to synthesize a
design?
- The DO's and DONT's
of Synthesis
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Mar 26
(Tuesday)
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- aliases, blocks, and
guarded blocks
- Discussion on how to create a
fifo
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Mar 28
(Thursday)
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- Lecture - Procedural
Behavioral BFMs for High Level Verfication
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April 2
(Tuesday)
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·
QUIZ 5 (procedures)
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April 4
(Thursday)
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- Frequently Asked
Questions in VHDL
- Overview of the Global
Coding Template
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April 9
(Tuesday)
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- Test 2 (70
minutes) – Jan 15 till date
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April 11
(Thursday)
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- Attributes in VHDL
- Bus keepers
- Timing Modelling
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April 16
(Tuesday)
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- Project device functional specifications to be turned
in today
- Topic TBD
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April 18
(Thursday)
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·
DO'S and DONT'S in VHDL
·
TBD
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April 23
(Tuesday)
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April 25
(Thursday)
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RESERVED
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April 30
(Tuesday)
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Review for Final Exam
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May 3
(Friday)
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FINAL
EXAM day – May 3, Friday. Time 7:40 AM to 9:30 AM – Venue: PSF173 (decided by Grad College. Date/time will be
changed)
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